The fabrication of integrated circuits relies heavily on lithographic processes. As the term is used herein, “integrated circuit” includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III-V compounds like gallium arsenide, or mixtures of such materials. The term includes all types of devices formed, such as memory and logic, and all designs of such devices, such as MOS and bipolar. The term also comprehends applications such as flat panel displays, solar cells, and charge coupled devices.
Lithography for current node sizes (45 nanometers and below) is particularly challenging. The integrated circuit designs at this size exhibit high reticle error enhancement factors, and can print reliably only over relatively narrow focus-exposure process windows. To ensure that the fabrication process is under control, a given number of the most challenging features within the design are selected for a detailed metrology analysis. These features are carefully measured, such as with a scanning electron microscope, and the results are analyzed to ensure that the substrates have been printed correctly. It is important to choose the most error-sensitive (fragile) features in the design, because this metrology analysis is used as an early detection system for any problems in the lithography process.
One problem is that modern integrated circuits have so many fragile features in their design that it is difficult to choose those that are the most valuable for the metrology analysis. Optical proximity compensation verification is currently used to determine the features on which to perform the metrology analysis. This is a method by which the design of the reticle, including the optical proximity compensation decorations, is input into a lithographic simulation to determine which features are particularly fragile. Those fragile features are then identified as candidates for the substrate metrology analysis.
The optical proximity compensation verification process tends to generate an extreme number of potential features, while providing relatively little information as to how to determine which of those potential features are the most valuable. To overcome this problem, more features than are really needed are selected for analysis, to try to get a reasonable statistical probability of selecting at least one of the more fragile features. This is time consuming and expensive. However, the most fragile features would not otherwise be selected out of the many thousands of identified features, so the earliest warning of process deviations would not otherwise be achieved using this method.
What is needed, therefore, is a method that overcomes problems such as those described above, at least in part.